1. Field of the Invention
The present invention relates to a reliable semiconductor design system and method for designing devices and circuits required and sufficient for a life of an electrical characteristic of a transistor used in a semiconductor apparatus having semiconductor elements. Furthermore, the present invention relates to a semiconductor apparatus designed by using the design system and method. In particular, the invention relates to a method for examining and estimating the life of a thin film transistor against hot carriers.
2. Description of the Related Art
One of typical physical phenomena relating to the life of a semiconductor element and a semiconductor apparatus is a characteristic deterioration phenomenon due to hot carriers. As a device size decreases, the electric field of the hot carriers increases locally. Therefore, the hot carriers become more important in the operation. As a result, the hot carriers cause the operational failures, reduction in operational functions and reduction in drain current to the drain voltage of the semiconductor apparatus, and the device characteristics and performance are deteriorated.
Here, the deterioration phenomena due to hot electrons will be described. When semiconductor elements, that is, a semiconductor apparatus is operated, a high electric field region is established near the drain region. Electrons flowed into the high electric field region become hot electrons having much higher energy. A part of the hot electrons may be implanted to a gate oxide film and may cause an interfacial level on the Si-SiO2. Thus, the element characteristics may be changed. Hot carriers are caused by positive holes and electrons, which are not in equilibrium and are higher than the grid temperature. Furthermore, substrate hot electrons exist in addition to the hot electrons of the channel electrons.
Carriers generated by collision ionization or avalanche multiplication may be implanted to an oxide film as hot carriers (drain avalanche hot carriers (DAHC)). Alternatively, hot electrons generated by secondary collision ionization may be implanted (secondarily generated hot electron (SGHE)). The details are described in “SUBMICRON DEVICES 2”, p. 121 to 142, Mitsumasa Koyanagi, Maruzen Kabushiki Kaisha Shuppan.
The reliability and characteristics of a semiconductor element and a semiconductor apparatus typically with respect to the deterioration due to the hot carriers may be examined and be evaluated by using a Test Element Group (TEG). TEG includes a circuit including multiple semiconductor elements on a test area mounted on a semiconductor chip.
A transient test is known as the examining method. The transient test is one of DC stress test methods. In the transient test, a DC voltage is applied with reference to a VG where the deterioration becomes the maximum. The DC stress test method is an examination method whereby a semiconductor element always receives a certain voltage. According to the DC stress test method, a single semiconductor element can be examined and the result can be obtained in a short period of time by applying a constant voltage to the single semiconductor element.
However, in a real semiconductor apparatus, the bias condition between terminals may change in accordance with the time. Thus, the type of-hot carriers may change. Therefore, the deterioration state may differ. Here, the change in type of hot carriers cause “easing of deterioration” and “promoting of deterioration”, for example. Both of them affect each other at the same time, and the real semiconductor apparatus exposes the significantly complicated deterioration.
In order to solve the problem, an AC stress test method is proposed in consideration of stress conditions (such as a bias condition and a duty ratio) applied to a real semiconductor apparatus. In the AC stress test Method, a ring oscillator (R.O.) or inverter chain having multiple TFT's are used for the evaluation as a TEG. A ring oscillator is a circuit in which an odd number of inverter circuits each having a CMOS structure are connected in a ring-shape. The ring oscillator is used for calculating a delay time for one inverter circuit. A method for examining a ring oscillator (R.O. ) is disclosed by Japanese Laid-Open Patent Applications No. 5-157799 and No. 7-325122. An inverter chain is multiple inverter circuit in CMOS structure and is disclosed in Japanese Laid-Open Patent Application No. 6-313787.
Alternative examining method is an aging test method. In the aging test method, a voltage, which is a predetermined stress, is applied to a real semiconductor apparatus (such as a module panel) under a predetermined environment (including a temperature and humidity). The real semiconductor apparatus is operated under the condition for a long period of time, and the minimum driving voltage and changes in current consumption due to the deterioration of the semiconductor apparatus are examined. Especially, the aging test for evaluating a panel may be called panel aging test.
The aging method can examine a semiconductor apparatus to evaluate the deterioration and characteristics. However, obtaining the evaluations may require several thousands of hours or several months as a test period.
On the other hand, a DC stress test method can be used for examining a semiconductor element in a short period of time to evaluate the deterioration and characteristics. However, the estimation and evaluation of the deterioration and characteristic obtained from the DC stress test method are different from those of a real semiconductor apparatus. The cause of the difference in estimation and evaluation is considered as that a constant voltage is applied as a stress in the DC stress test method while a real stress applied to a semiconductor apparatus is an alternate-current voltage (pulse voltage).
Even when an alternate current voltage (pulse voltage) is applied to a semiconductor apparatus as a stress in the AC stress test, a difference may occur in results of the examinations on semiconductor apparatuses. This is because the stress occurring in a real semiconductor apparatus cannot be evaluated and be considered accurately enough. Therefore, estimating the accurate deterioration and characteristics of a semiconductor apparatus has been difficult.
In this way, the estimation of the deterioration and characteristics based on a result of a DC stress test method or an AC stress test method does not always and simply correspond to the estimation of those of a semiconductor apparatus. Furthermore, the correlation between these tests is not clear.